1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to a mechanism for use during diagnostic operations performed upon integrated circuits, such as, for example, debug, trace and manufacturing test.
2. Description of the Prior Art
With the increase in complexity of integrated circuits there is an increasing need for thorough and efficient diagnostic mechanisms. These diagnostic mechanisms may be used to identify design or programming errors through techniques such as debugging and tracing. Further diagnostic techniques may be used to identify whether a particular integrated circuit has been manufactured correctly as part of manufacturing test operations. In order to provide communication with these on-chip diagnostic mechanisms, it is known to provide dedicated or dual purpose integrated circuit pins which can be used to insert data to, remove data from, control and otherwise interact with the diagnostic mechanisms concerned. Depending upon the bandwidth required for this communication, it may be necessary to provide a large number of such pins to enable appropriate communication.
As the complexity of integrated circuits has increased there has also been a trend to requiring an increased pin count on integrated circuit packages. This is a difficult technical challenge and the pin count available is often a design constraint for integrated circuits. Furthermore, each pin on an integrated circuit also has to have an appropriate connection in the external system to which it can be attached and the provision of such connections as well as the need to make the attachment tends to increase manufacturing costs. These manufacturing cost issues can be particularly severe within applications such as micro-controllers where it is important that the devices and their associated larger systems should be as inexpensive as practical. A requirement for increased pin count may also result in a need to step up from one integrated circuit package size with a given available pin count to a larger, more expensive integrated circuit package size so as to increase the available pin count to meet the total requirements including appropriate diagnostic connections.